The present invention relates generally to a voltage- or current-controlled oscillator and, more particularly, relates to a voltage- or current-controlled relaxation oscillator having a programmable gain.
Many electrical and computer applications and components have critical timing requirements that compel generation of periodic clock waveforms that are precisely synchronized with a reference clock waveform. A phase-locked loop (xe2x80x9cPLLxe2x80x9d) is one type of circuit that is widely used to provide an output signal having a precisely controlled frequency that is synchronous with the frequency of a reference or input signal. Wireless communication devices, frequency synthesizers, multipliers and dividers, single and multiple clock generators, and clock recovery circuits are but a few examples of the manifold implementations of PLLs.
Frequency synthesis is a particularly common technique used to generate a high frequency clock from a lower frequency reference clock. In microprocessors, for example, an on-chip PLL can multiply the frequency of a low frequency input (off-chip) clock, typically in the range of 1 to 4 MHz, to generate a high frequency output clock, typically in the range of 10 to over 200 MHz, that is precisely synchronized with the lower frequency external clock. Another common use of PLLs is recovery of digital data from serial data streams by locking a local clock signal onto the phase and frequency of the data transitions. The local clock signal is then used to clock a flip-flop or latch receiving input from the serial data stream.
FIG. 1 is a block diagram of a typical PLL 10. PLL 10 comprises phase/frequency detector 12, charge pump 14, loop filter 16, voltage-controlled oscillator (xe2x80x9cVCOxe2x80x9d) 18 and frequency divider 20. PLL 10 receives a reference clock signal CLKREF and generates an output clock signal CLKOUT aligned to the reference clock signal in phase. The output clock frequency is typically an integer (N) multiple of the reference clock frequency; with the parameter N set by frequency divider 20. Hence, for each reference signal period, there are N output signal periods.
Phase/frequency signal detector 12 receives on its input terminals two clock signals CLKREF and CLK*OUT (CLKOUT, with its frequency is divided down by frequency divider 20). In a conventional arrangement, detector 12 is a rising edge detector that compares the rising edges of the two clock signals. Based on this comparison, detector 12 generates one of three states. If the phases of the two signals are aligned, the loop is xe2x80x9clockedxe2x80x9d. Neither the UP nor the DOWN signal is asserted and VCO 18 continues to oscillate at the same frequency. If CLKREF leads CLK*OUT, than VCO 18 is oscillating too slowly and detector 12 outputs an UP signal proportional to the phase difference between CLKREF and CLK*OUT. Conversely, if CLKREF lags CLK*OUT, than VCO 18 is oscillating too quickly and detector 12 outputs a DOWN signal proportional to the phase difference between CLKREF and CLK*OUT. The UP and DOWN signals typically take the form of pulses having a width or duration corresponding to the timing difference between the rising edges of the reference and output clock signals.
Charge pump 14 generates a current ICP that controls the oscillation frequency of VCO 18. ICP is dependent on the signal output by phase/frequency detector 12. If charge pump 14 receives an UP signal from detector 12, indicating that CLKREF leads CLK*OUT, ICP is increased. If charge pump 14 receives a DOWN signal from detector 12, indicating that CLKREF lags CLK*OUT, ICP is decreased. If neither an UP nor a DOWN signal is received, indicating that the clock signals are aligned, charge pump 14 does not adjust ICP.
Loop filter 16 is positioned between charge pump 14 and VCO 18. Application of the charge pump output current ICP to loop filter 16 develops a voltage VLF across filter 16. VLF is applied to VCO 18 to control the frequency of the output clock signal. Filter 16 also removes out-of-band, interfering signals before application of VLF to VCO 18. A common configuration for a loop filter in a PLL is a simple single-pole, low-pass filter that an be realized with a single resistor and capacitor.
The oscillator is the subject of the present invention. VCO 18 generates an oscillating output signal CLKOUT having a frequency proportional to the voltage VLF applied to VCO 18. Conventional voltage-controlled oscillators typically oscillate about a specific center frequency and have a relatively narrow frequency range or bandwidth. When CLKREF leads CLK*OUT, charge pump 14 increases ICP to develop a greater VLF across loop filter 16 which, in turn, causes VCO 18 to increase the frequency of CLKOUT. Conversely, When CLKREF lags CLK*OUT, charge pump 14 decreases ICP to develop a lesser VLF across loop filter 16 which, in turn, causes VCO 18 to decrease the frequency of CLKOUT. When CLKREF and CLK*OUT are aligned, VLF is not adjusted, and the oscillation frequency of VCO 18 is kept constant. In this state, PLL 10 is in a xe2x80x9clockedxe2x80x9d condition.
The output clock signal is also looped back through (in some applications) frequency divider 20. The resultant output CLK*OUT is provided to phase/frequency detector 12 to facilitate the phase-locked loop operation. Frequency divider 20 facilitates comparison of the generally higher frequency output clock signal with the lower frequency reference clock signal by dividing the frequency of CLKOUT by the multiplication factor N. Divider 20 may be implemented using trigger flip-flops, or through other methods familiar to those of ordinary skill in the art. Thus, PLL 10 compares the reference clock phase to the output clock phase and eliminates any detected phase difference between the two by adjusting the frequency of the output clock.
Fully monolithic phase-locked loops formed from complementary metal-oxide-semiconductor (xe2x80x9cCMOSxe2x80x9d) field effect transistors (xe2x80x9cFETxe2x80x9d) are widely used in many applications. The widespread industrial capability to mass-produce CMOS circuits facilitates the manufacture of inexpensive basic tuning devices employing PLLs for products such as wireless telephones. Since the power consumption of the PLL derives primarily from the on-chip oscillator, the power consumed by the PLL increases as the operating frequency of the oscillator increases. The goal of achieving high frequency operation is thus inconsistent with low power consumption. In addition to lower power consumption, an oscillator having a wide linear range is desirable for optimal PLL performance. Accordingly, there is a need for a low power, high frequency oscillator that has a wide linear range and is designed with CMOS technology.
FIGS. 2a, 2b and 2c depict three CMOS oscillator architectures. FIG. 2a depicts a CMOS-based differential ring oscillator 30. Ring oscillator 30 is comprised of a plurality of differential inverters 32 connected in cascade, with the output of the last inverter in the series being connected to the input of the first inverter. This oscillator design is problematic in that it is very sensitive to process and temperature variations. The nominal output frequency of a conventional CMOS differential ring oscillator, for example, may range from 700 MHz to 1.3 GHz. This represents almost a 100% frequency variation. This sensitivity stems from the inverse relationship between the delay time of the inverters and the output frequency. A PLL based on a ring oscillator requires an increased VCO gain in order to obtain the necessary range to deal with these wide frequency variations. The increased VCO gain leads to poor phase performance and increased sensitivity.
FIG. 2b depicts a typical relaxation oscillator 40 having a grounded timing capacitor 42. Current sources 46 and 48 together provide a switching current i=xc2x1kvin, where vin is a control voltage for capacitor 42. The voltage developed across capacitor 42, Vc, is applied to Schmitt trigger circuit 44. When i=+kvin, current source 46 is connected, and capacitor 42 begins to charge. Trigger circuit 44 generates an output voltage vo that remains a logical one until vc reaches the high threshold voltage vH of Schmitt trigger 44. At this time, vo drops to a logical zero, current sources 46 and 48 are switched such that i=xe2x88x92kvin, and capacitor 42 begins to discharge. As capacitor 42 is discharging, vo remains a logical zero until vc reaches the low threshold voltage vL of Schmitt trigger 44. At this time, vo jumps back to a logical one, current sources 46 and 48 are switched such that i=+kvin, and capacitor 42 begins to recharge. In this manner, an oscillating output is produced, with the charging and discharging time of capacitor 42 constituting a period.
The frequency of oscillator 40 is dependent upon and characterized by the current provided by current sources 46 and 48, the capacitance of capacitor 42, and the reference voltage. Accordingly, relaxation oscillator 40 is less sensitive to process and temperature variations relative to the CMOS-based differential ring oscillator described above. As the capacitance increases, however, the discharging operation takes longer and consequently, the attainable frequency and sensitivity of oscillator 40 decreases. Moreover, at high speeds, the delay time introduced by Schmitt trigger 44 plays a significant role in determining the oscillation period.
FIG. 2c shows a source-coupled, current-controlled relaxation oscillator 60 with a floating timing capacitor 62. Oscillator 60 includes a pair of n-channel CMOS transistors M3 and M4 having their gates and drains coupled to supply voltage VDD, and their sources coupled to, respectively, the drains of n-channel CMOS transistors M1 and M2. The gate of M1 is cross-coupled to the source of M4, and the gate of M2 is cross-coupled to the source of M3. Timing capacitor 62 is connected between the sources of transistors M1 and M2 and grounded current sources 64 and 66.
Oscillator 60 generates oscillating output voltages VO1 and VO2 as follows. In an initial state, with transistor M1 off and transistor M2 on, no current flows through transistor M1 and the current flowing through transistor M2 is 2I. Assuming that the current is large enough to turn transistor M4 on, and neglecting gate currents, the current flowing through transistor M4 is also 2I. Accordingly, the voltage VO2 is at least one threshold drop below supply voltage VDD. Conversely, since transistors M1 and M3 (by virtue of M1 being off) are off, no current flows through these transistors and the output voltage VO1 is essentially equal to the supply voltage VDD.
In this initial condition, a current I passes through capacitor 62 in the direction towards current source 64, and begins to charge capacitor 62. As capacitor 62 charges, the source of transistor M1 gradually becomes more negatively charged. Eventually, the gate-to-source voltage drop across transistor M1 becomes great enough to turn transistor M1 on. The resulting voltage drop at the source of transistor M3 also turns transistor M3, and the voltage drop at the gate of transistor M2 (through its coupling to the source of transistor M3) turns transistors M2 and M4 off. A current 2I now flows through transistors M3 and M1, and a current I flows through capacitor 62 in the opposite direction (towards current source 66). By virtue of the current flow, the output voltage VO1 drops from VDD. When that voltage has dropped to at least the threshold voltage below VDD, transistors M1 and M3 turn on, and transistors M2 and M4 turn off. As no current flows through transistors M4 and M2, the output voltage VO2 rises to VDD. Capacitor 62 begins discharge until the voltage at the source of transistor M2 becomes negative enough to turn transistor M2 on. In this manner, output voltages VO1 and VO2 take the form of oscillating square waves (180xc2x0 out-of-phase). The oscillation frequency is determined largely by the capacitance of capacitor 62.
A relaxation oscillator having a floating timing capacitor, as illustrated and described with reference to FIG. 2c, presents several advantages. It has only one stage, its symmetric architecture minimizes power consumption, and its differential operation provides a fifty percent duty cycle, which is a desirable attribute in those applications in which the elimination of even harmonics is important. A control voltage from a loop filter is passed through a voltage-to-current converter (not shown), and the voltage-to-current converter outputs a current I. Due to the use of nonlinear load transistors M3 and M4, however, oscillator 60 exhibits a highly nonlinear voltage-to-frequency characteristic. This nonlinear characteristic makes it difficult to control the output frequency by varying I, and also makes it difficult to control the gain or sensitivity. This problem is magnified when CMOS technology is used, since the CMOS diode characteristic is poorer than the bipolar diode characteristic. For these reasons, this architecture is generally not viewed as suitable for CMOS oscillators.
In view of the above, there is a need for a low-power, low-noise CMOS oscillator with an improved voltage-to-frequency characteristic and a more precisely controllable output frequency.
In accordance with the purpose of the invention as broadly described herein, there is provided a relaxation oscillator. The oscillator has a simple and symmetric structure, a digitally programmable gain and may be voltage- or current-controlled.
In a first embodiment of the present invention, an oscillator comprises a slope-fixing circuit that generates a control signal and fixes the slope of the control signal. The oscillator further comprises a swing-fixing circuit that fixes the swing of the control signal, and a switching block that generates an output signal. The output signal has a frequency derived from the swing and the slope of the control signal.
In one implementation of the first embodiment, the slope-fixing circuit comprises a fixed timing capacitor C1 and a plurality of switchable timing capacitors C2 . . . CN. The effective capacitance C is programmable through the placement of selected ones of timing capacitors C2 . . . CN in parallel with fixed timing capacitor C1. The slope of the control signal is determined by the ratio of a control current I to the effective capacitance C. The swing-fixing circuit comprises a replica cell that provides a fixed voltage swing VSW, and a pair of load transistors that the voltage swing is applied across. The voltage swing VSW is programmable by setting a reference voltage VREF, which is provided to the gates of the load transistors by the replica cell, to one of a plurality of incremental reference voltages VREF1 . . . VREFM. The voltage swing VSW is given by the difference between a supply voltage VDD and the reference voltage, VSW=VDDxe2x88x92VREF. The switching block comprises a pair of switching transistors that alternate between xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d states depending on the value of the control signal to produce an oscillating output signal. The frequency of the output signal is given by       I          4      ⁢              CV        SW              .
In second embodiment of the present invention, a relaxation oscillator integrated on a single semiconductor chip is provided. It comprises a voltage-to-current converter for generating a control current I from an input voltage. A current-controlled oscillator generates an oscillating output signal from the control current I and an internal control signal. The current-controlled oscillator comprises at least one timing capacitor having an effective capacitance C that fixes the slope of the control signal as I/C. A pair of load transistors fixes the voltage swing VSW of the control signal. A pair of switching transistors coupled between the at least one capacitor and the load transistors generates the oscillating output signal based on the internal control signal. The relaxation oscillator further comprises a replica cell that provides a reference voltage VREF to the load transistors to fix the voltage swing VSW across the load transistors.
In one implementation of the second embodiment, the voltage-to-current converter comprises a control transistor having its gate coupled to the input voltage and a resistor coupled between the source of the transistor and ground for generating the control current I. A cascoded transistor current mirror mirrors the control current I from the voltage-to-current converter to the current-controlled oscillator. The replica cell comprises an operational amplifier that accepts the reference voltage VREF and regulates the load transistors of the current controlled oscillator to maintain the voltage swing VSW at a fixed value.
A third embodiment of the present invention provides a phase-locked loop. The phase-locked loop comprises a phase/frequency detector that compares a reference clock signal with an output clock signal and generates an appropriate charge pump control voltage. A charge pump is coupled to the phase/frequency detector and generates a loop filter control current from the charge pump control voltage. A loop filter is coupled to the charge pump and generates a loop filter voltage from the loop filter control current. An oscillator is coupled to the loop filter. The oscillator comprises a slope-fixing circuit that receives the loop filter voltage and generates a control signal having a fixed slope, a swing-fixing circuit that fixes the swing of the control signal; and a switching block that generates the output clock signal. The output clock signal has a frequency derived from the swing and slope of the control signal. A feedback circuit is coupled between the oscillator and the phase/frequency detector and provides the output clock signal to the phase/frequency detector.
In one implementation of the third embodiment, the slope-fixing circuit comprises a fixed timing capacitor C1 and a plurality of switchable timing capacitors C2 . . . CN that provides an effective capacitance C. A current supply provides a control current I, yielding a control signal having a slope I/C. The feedback circuit comprises a frequency divider that divides the frequency of the output clock signal by a division factor N. The division factor N is provided by a programming signal. This implementation further comprises a decoder coupled to the oscillator that also receives the programming signal. Based on the programming signal, the decoder programs the slope-fixing means to generate a particular effective capacitance C.
In one method according to the present invention, an oscillating output signal VO is generated. The method comprises the following steps:
(a) fixing a voltage swing VSW across a variable resistance load;
(b) fixing an effective timing capacitance C;
(c) providing a control current I;
(d) deriving a control signal slope from the control current I and the effective timing capacitance C;
(e) setting a control signal VC to an initial value based on the voltage swing
(f) outputting the signal VO at an initial level or at a switched level;
(g) decreasing the control signal VC along the control signal slope;
(h) continuing to output the signal VO at the current level as long as the change in the control voltage xcex94VC does not exceed a threshold voltage VT ;
(i) switching the level of the output signal VO when xcex94VC exceeds the threshold voltage VT ;
(j) repeating the method beginning with step (e) if the control current I has not changed; and
(k) repeating the method beginning with step (d) if the control current I has changed.
In an implementation of this method, the voltage swing VSW is fixed according to the relationship VSW=VDDxe2x88x92VREF, wherein VDD is a supply voltage and the reference voltage VREF is digitally programmable from a range of incremental reference voltages VREF1 . . . VREFM to yield a corresponding range of swing voltages. The effective timing capacitance C is fixed by placing appropriate switchable timing capacitors C2 . . . CN in parallel with a fixed capacitor C1.
In another method according to the present invention, a method for programming the gain or sensitivity KO of an oscillator, wherein             K      0        =          1              4        ⁢                  CV          SW                      ,
is provided. The method includes the steps of determining the desired gain KO, coarse-tuning the oscillator by selecting an effective capacitance C to achieve the desired gain KO and fine-tuning the oscillator by selecting a voltage swing VSW to achieve the desired gain KO.
Objects and advantages of the present invention include any of the foregoing, singly or in combination. Further objects and advantages will be apparent to those of ordinary skill in the art, or will be set forth in the following disclosure.